The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a read only memory ("ROM") cell, and more particularly to the manufacture of a flash electrically-erasable programmable read only memory ("Flash EEPROM") cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as mask ROMs, microcontrollers, microprocessors ("MICROs"), digital signal processors ("DSPs"), application specific integrated circuits, among others.
Read only memories (ROMs) and various methods of their manufacture are known in the art. In the fabrication of a ROM, particularly an EEPROM, it is necessary to fabricate a storage cell that maintains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a stored charge on a "floating" gate of a storage cell transistor. Specifically, the storage cell includes at least two conducting layers--one conducting layer is the floating gate of the storage cell transistor, and another conducting layer is the control gate for control of the cell operation--which may be, for example, polysilicon. In a typical device, the floating gate is formed on a thin gate oxide formed on the substrate, and the control gate is located above the floating gate. In such a device, the control gate and floating gate are isolated each other by a thin dielectric layer known as an "interpoly oxide", which may typically be composed of oxide/nitride/oxide ("ONO"). In some typical EEPROMs, data is programmed into the cells by applying a high voltage to the control gate to inject hot electrons (or tunnel electrons in some devices) into the floating gate. The process of programming data is often called coding. In coding, the charge is transferred from the silicon substrate through the thin gate oxide layer to the floating gate.
In typical EEPROMs, especially for flash EEPROMs, two different gate oxide thicknesses are required for optimized device performance. In such devices, it is critical to grow a high-quality, thin gate oxide (used as a tunneling oxide) in the storage cell and a thick gate oxide in transistors in the periphery of the storage cell region in order to provide high driving capability for higher speed. Controlling the thickness of the thin gate oxide is crucial, especially since design rules for devices with gates are becoming increasingly smaller and require thinner gate oxides. However, because high-voltage supplies are used, thicker gate oxides at the periphery and the storage cell region are needed to maintain device quality and reliability after long-term high voltage stress from the high voltages (e.g., up to or greater than +12V) generated through a pumping circuit for the storage cell coding and/or erase. Therefore, implementing different gate oxide thicknesses in EEPROM devices is an important aspect of the fabrication of high performance devices.
Prior art methods for forming different gate oxide thicknesses in ROMs have typically involved the use of photoresist in combination with either a dry or wet etch step. First, a thick gate oxide is grown on a silicon substrate and masked with a photoresist. The photoresist used makes physical contact with and masks a portion of the thick gate oxide, while the etch step removes some of the gate oxide to provide a thinner gate oxide. Such photoresist typically contains many contaminants which degrade the ability of the thick gate oxide to resist long-term high voltage stresses. Moreover, use of a dry etch creates the possibility of over-etching in some portions of the gate oxide down to the silicon substrate to damage the substrate and degrade the quality of the gate oxide layer. Even if the dry etch does not over-etch, the use of a dry etch may also present problems for gate oxide quality and oxide thickness control.
From the above it is seen that an improved method of fabricating semiconductor ROM devices with a reliable, high-quality gate oxide having different thicknesses is often desired. Further, improved methods are needed which are able to provide with adequate thickness control high-quality gate oxides, especially for increasingly smaller device dimensions, that are sufficiently thin in certain regions such as in the cell regions and in periphery regions and thicker in other regions such as periphery regions.